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the GM71V18163CJ-6E is the new generation dynamic ram organized 1,048,576 x 16 bit. GM71V18163CJ-6E has realized higher density, higher performance and various functions by utilizing advanced cmos process technology. the GM71V18163CJ-6E offers extended data out(edo) mode as a high speed access mode. multiplexed address inputs permit the GM71V18163CJ-6E to be packaged in standard 400 mil 42pin plastic soj. the package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. description features * 1,048,576 words x 16 bit organization * extended data out mode capability * single power supply (3.3v+/-0.3v) * fast access time & cycle time ( unit: ns) pin configuration 1,048,576 words x 16 bit edo dram-et part GM71V18163CJ-6E t rac t cac t rc t hpc 60 15 104 25 * low power active : 684/612/540mw (max) standby : 7.2mw (cmos level : max) 0.83 mw (l-version : max) * /ras only refresh, /cas before /ras refresh, hidden refresh capability * all inputs and outputs ttl compatible * 1024 refresh cycles/16ms * 2 cas byte control ( top view) GM71V18163CJ-6E v ss i/o15 i/o14 i/o13 i/o12 38 39 40 41 42 i/o11 i/o10 i/o9 i/o8 nc 32 33 34 35 36 v ss 37 / lcas / ucas / oe 29 30 31 a9 a8 a7 26 27 28 a6 a5 a4 23 24 25 v ss 22 v cc i/o0 i/o1 i/o2 i/o3 1 2 3 4 5 i/o4 i/o5 i/o6 i/o7 nc 7 8 9 10 11 v cc 6 nc / we / ras 12 13 14 nc nc a0 15 16 17 a1 a2 a3 18 19 20 v cc 21 42 soj rev 0.1 / apr ? 01
GM71V18163CJ-6E pin description pin function pin function a0-a9 a0-a9 i/o0-i/o15 / ras / we v cc v ss nc address inputs refresh address inputs data-in/out row address strobe read/write enable power (+3.3v) ground no connection ordering information column address strobe / oe output enable absolute maximum ratings* type no. access time package gm71v18163cj ? 6e 60 ns 400 mil 42 pin plastic soj symbol parameter rating unit t a t stg v in/out v cc i out -30 ~ 85 -55 ~ 125 -0.5 ~ vcc +0.5 (<=4.6v(max)) -0.5 ~ 4.6 50 ambient temperature under bias storage temperature voltage on any pin relative to v ss supply voltage relative to v ss short circuit output current v v ma p d 1.0 power dissipation w c c / ucas, /lcas note: operation at or above absolute maximum ratings can adversely affect device reliability. rev 0.1 / apr ? 01
GM71V18163CJ-6E truth table / ras / lcas / ucas / we / oe h l l l d h l h d h h l d h h h d d l l output open valid valid valid lower byte upper byte word operation standby / ras-only refresh cycle read cycle l l l l l l h l h early write cycle l h l l h open open open l l l l undefined delayed write cycle l l l h h h to l l cbr refresh or self refresh (l-series) h to l h l h to l l l notes 1,3 1,3 1,3 1,3 1,3 1,2,3 1,2,3 1,3 lower byte upper byte word lower byte upper byte word lower byte upper byte word undefined undefined open open open open open valid valid valid word word word word read-modify -write cycle read cycle (output disabled) d d h to l h to l h to l l l l l l l l h l l l l h d d l h h h h l d d d d d d l to h l to h l to h l l l l recommended dc operating conditions (ta = -30 ~ 85c) symbol parameter unit v cc v ih v il supply voltage input high voltage input low voltage v v v max 3.6 v cc + 0.3 0.8 typ 3.3 - - min 3.0 2.0 -0.3 note: all voltage referred to vss . the supply voltage with all vcc pins must be on the same level. the supply voltage with all vss pins must be on the same level. notes: 1. h: high (inactive) l: low(active) d: h or l 2. t wcs >= 0ns early write cycle t wcs <= 0ns delayed write cycle 3. mode is determined by the or function of the /ucas and /lcas. (mode is set by earliest of /ucas and /lcas active edge and reset by the latest of /ucas and /lcas inactive edge.) however write operation and output high-z control are done independently by each /ucas, /lcas. ex) if /ras = h to l, /ucas = h, /lcas = l, then /cas-before-/ras refresh cycle is selected. rev 0.1 / apr ? 01
GM71V18163CJ-6E dc electrical characteristics (vcc = 3.3v+/-0.3v, vss = 0v, ta = -30 ~ 85c) symbol parameter note v oh v ol output level output "h" level voltage (i out = -2 ma ) unit v v max v cc 0.4 min 2.4 0 output level output "l" level voltage (i out = 2 ma ) i cc1 operating current average power supply operating current (/ras, /ucas or /lcas cycling : t rc = t rc min) i cc2 standby current (ttl) power supply standby current (/ras, /ucas, /lcas = v ih , d out = high-z) i cc3 ras only refresh current average power supply current ras only refresh mode ( t rc = t rc min) i cc4 i cc5 standby current (cmos) power supply standby current (/ras, /ucas or /lcas >= v cc - 0.2v, d out = high-z) i cc6 / cas-before-/ras refresh current ( t rc = t rc min) i cc7 i l(i) ua 10 -10 i l(o) ua 10 -10 input leakage current any input (0v <= v in <= 4.6v) output leakage current (d out is disabled, 0v <= v out <= 4. 6v) edo page mode current average power supply current edo page mode ( t hpc = t hpc min) note: 1. i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2. address can be changed once or less while /ras = v il . 3. address can be changed once or less while /lcas and /ucas = v ih . 4. /ucas = l (<=0.2) and /lcas = l (<=0.2) while /ras = l (<=0.2). battery back up operating current(standby with cbr ref.) (cbr refresh, t rc =125us , t ras <= 0.3 us, d out = high-z, cmos interface) 400 - 4,5 ua i cc8 i cc9 ua self-refresh mode current (/ras, /ucas or /lcas<=0.2v , d out = high-z) 250 - 5 ma 2 - ma 1 - 150 - ua ma 1, 2 ma 2 ma 1, 3 ma 5 - 5 1 ma standby current /ras = v ih /u cas, /lcas = v il d out = enable 60 ns 170 - 60 ns 170 - 60 ns 165 - 60 ns - 170 rev 0.1 / apr ? 01
GM71V18163CJ-6E capacitance (vcc = 3.3v +/- 0.3v, ta = 25 c ) symbol parameter note c i1 c i2 c i/o input capacitance (address) input capacitance (clocks) output capacitance (data-in/out) 1 1 1, 2 unit pf max 5 7 7 min - - - note: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. /ucas and /lcas = v ih to disable d out . ac characteristics (vcc = 3.3v+/-0.3v, ta = -30 ~ +85c, note 1, 2, 18, 19, 20) test conditions input rise and fall times : 2 ns output timing reference levels : 0.8v, 2.0v input levels : v il = 0v, v ih = 3v output load : 1ttl gate + c l (100 pf ) input timing reference levels : 0.8v, 2.0v (including scope and jig) pf pf read, write, read-modify-write and refresh cycles (common parameters) symbol parameter note unit max min t rc random read or write cycle time 104 - t rp / ras precharge time 40 - t ras / ras pulse width 60 10,000 t cas / cas pulse width 10,000 10 t asr row address set up time - 0 t rah row address hold time - 10 t asc column address set-up time - 0 t cah column address hold time - 10 t rcd / ras to /cas delay time 45 14 3 t rad / ras to column address delay time 30 12 4 t rsh / ras hold time - 13 t csh / cas hold time - 40 t crp / cas to /ras precharge time - 5 t t transition time (rise and fall) 50 2 7 t dzo / oe delay time from d in - 0 t dzc / cas delay time from d in - 0 / oe to d in delay time - 15 5 6 6 t cp / cas precharge time 10 - t odd GM71V18163CJ-6E ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 21 21 22 23 rev 0.1 / apr ? 01
GM71V18163CJ-6E read cycle symbol parameter note max unit min t rac access time from /ras - 60 t cac access time from /cas - 15 t aa access time from address - 30 t rcs read command setup time 0 - t rch read command hold time to /cas 0 - 8,9 9,10,17 9,11,17 - 15 9 12,22 access time from /oe GM71V18163CJ-6E t oac t rrh 5 - 12 t ral column address to /ras lead time 30 - read command hold time to /ras t off output buffer turn-off time 15 13,27 - t cal column address to /cas lead time 18 - t clz / cas to output in low-z 0 - t oez output buffer turn-off time to /oe 15 13 - t oh output data hold time 3 - t oho output data hold time from /oe 3 - t cdd / cas to d in delay time 15 - 5 t rchr t ohr t ofr t wez t wdd t rdd read command hold time from /ras 60 output data hold time from /ras 3 output buffer turn off to /ras output buffer turn off to /we / we to d in delay time / ras to d in delay time 15 15 15 - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 21 27 27 27 rev 0.1 / apr ? 01
GM71V18163CJ-6E write cycle symbol parameter note max unit min t wcs 0 - t wch 10 - t wp 10 - t rwl 10 - t cwl 10 - t ds 0 - t dh 10 - 15,23 15,23 write command setup time write command hold time write command pulse width write command to /ras lead time write command to /cas lead time data-in setup time data-in hold time 14,21 GM71V18163CJ-6E read- modify-write cycle symbol parameter note max unit min t rwc 136 - t rwd 79 - t cwd 34 - t awd 49 - 14 14 14 t oeh 15 - read-modify-write cycle time / ras to /we delay time / cas to /we delay time column address to /we delay time / oe hold time from /we GM71V18163CJ-6E ns ns ns ns ns ns ns ns ns ns ns ns 21 23 refresh cycle symbol parameter note max unit min t csr 5 - ns t chr 10 - ns t rpc 5 - ns / cas setup time (/cas-before-/ras refresh cycle) / cas hold time (/cas-before-/ras refresh cycle) / ras precharge to /cas hold time 21 22 21 GM71V18163CJ-6E rev 0.1 / apr ? 01
GM71V18163CJ-6E symbol parameter note max unit min t hpc 25 - t rasp t acp 35 - t rhcp 9,17,22 - 16 100,000 - 35 GM71V18163CJ-6E edo page mode cycle 25 t doh t col t cop t rchp 3 - - - - 9 10 5 35 ns ns ns ns ns ns ns ns access time from /cas precharge / ras hold time from /cas precharge edo page mode /ras pulse width edo page mode cycle time output data hold time from /cas low / cas hold time referred /oe / cas to oe setup time read command hold time from /cas precharge edo page mode read-modify-write cycle symbol parameter note max unit min t hprwc 68 - ns t cpw 54 - ns 14,22 edo page mode read-modify-write cycle time / we delay time from /cas precharge refresh symbol parameter note max unit min t ref 16 - ms refresh period 1024 cycles GM71V18163CJ-6E GM71V18163CJ-6E rev 0.1 / apr ? 01
GM71V18163CJ-6E 1. ac measurements assume t t = 2 ns. 2. an initial pause of 200us is required after power followed by a minimum of eight initializa - tion cycles (any combination of cycles containing /ras-only refresh or /cas-before-/ras refresh). 3. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 4. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 5. either t odd or t cdd must be satisfied. 6. either t dzo or t dzc must be satisfied. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih (min) and v il (max). 8. assumes that t rcd <= t rcd (max) and t rad <= t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 9. measured with a load circuit equivalent to 1ttl loads and 100pf. 10. assumes that t rcd >= t rcd (max) and t rad <= t rad (max). 11. assumes that t rcd <= t rcd (max) and t rad >= t rad (max). 12. either t rch or t rrh must be satisfied for a read cycles. 13. t off (max) and t oez (max) define the time at which the outputs achieve the open circuit condi - tion and are not referred to output voltage levels. 14. t wcs , t rwd , t cwd , t awd and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only; if t wcs >= t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit(high impedance) throughout the entire cycle; if t rwd >= t rwd (min), t cwd >= t cwd (min), and t awd >= t awd (min), or t cwd >= t cwd (min) t awd >= t awd (min) and t cpw >= t cpw (min), the cycle is a read-modify-write and the data out- put will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. notes : rev 0.1 / apr ? 01
GM71V18163CJ-6E 15. these parameters are referred to /ucas and /lcas leading edge in early write cycles and to /we leading edge in delayed write or read-modify-write cycles. 16. t rasp defines /ras pulse width in edo mode cycles. 17. access time is determined by the longer of t aa or t cac or t acp . 18. in delayed write or read-modify-write cycles, /oe must disable output buffer prior to applying data to the device. after /ras is reset, if t oeh >= t cwl , the i/o pin will remain open circuit (high impedance): if t oeh <= t cwl , invalid data will be out at each i/o. 19. when both /lcas and /ucas go low at the same time, all 16-bits data are written into the device. /lcas and /ucas cannot be staggered within the same write/read cycles. 20. all the vcc and vss pins shall be supplied with the same voltages. 21. t asc , t cah , t rcs , t wcs , t wch , t csr and t rpc are determined by the earlier falling edge of /ucas or /lcas. 22. t crp , t chr , t rch , t acp and t cpw are determined by the later rising edge of /ucas or /lcas. 23. t cwl , t dh , t ds and t chs should be satisfied by both /ucas and /lcas. 24. t cp is determined by the time that both /ucas and /lcas are high. 25. t hpc (min) can be achieved during a series of edo page made write cycles or edo mode write cycles. it both write and read operation are mixed in a edo mode ras cycle(edo mode mix cycle (1),(2)) minimum value of cas cycle ( t cas + t cp +2tt) becomes greater than the specified t hpc (min) value. the value of cas cycle time of mixed edo mode is shown in edo mode mix cycle (1) and (2). 26. when output buffers are enabled once, sustain the low impedance state until valid data is obtained. when output buffer is turned on and off within a very short time , generally it causes large vcc / vss line noise, which causes to degrade v ih min/v il max level. 27. data output turns off and becomes high impedance from later rising edge of ras and cas. hold time and turn off time are specified by the timing specification of later rising edge of ras and cas between t ohr and t oh , and between t ofr and t off . 28. edo hi-z control by oe or we. oe rising edge disables data outputs. when oe goes high during cas high, the data will not come out until next cas access. when we goes low during cas high, the data will not come out until next cas access. 29. please do not use t rass timing, 10us<= t rass <=100us. during this period, the device is in transition state from normal operation mode to self refresh mode. if t rass >=100us, then ras 30. h or l ( h : v ih (min) <= v in <= v ih (max), l : v il (min) <= v in <= v il (max) ) rev 0.1 / apr ? 01
GM71V18163CJ-6E package dimension 42 soj unit: inches (mm) 1.072(27.23) max 0.395(10.03) min 0.435(11.06) min 0.445(11.30) max 0.148(3.75) max 0.128(3.25) min 0.026(0.66) min typ 0.050(1.27) 0.405(10.29) max 0.020(0.50) max 0.015(0.38) min 1.058(26.89) max 0.360(9.15) min 0.380(9.65) max 0.025(0.64) min 0.093(2.38) min 0.032(0.81) max rev 0.1 / apr ? 01

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